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| tx3927 TMPR3927 specification update revision history 23-may-2001 rev1.0 initial release (up to ert-tx3927-008) 04-oct-2001 rev1.1 added ert-tx3927-009 and ert-tx3927-010 added ce* to ert-tx3927-008. added the table ?summary of the differences among versions of the tx3927.? added descriptions to the document changes table. 30-oct-2002 rev1.2 deleted condition 3 of ert-tx3927-008. modified the description for wince in ert-tx3927-009. added descriptions to the document changes table. 22-jan-2002 rev1.3 added a description of TMPR3927cf. added ert-tx3927-011 to ert-tx3927-014. 05-jul-2003 rev1.4 added ert-tx3927-015 to ert-tx3927-017. modified a note showing product types in ert-tx3927-009. added descriptions to the document changes table. changed hard hat linux to monta vista linux. 14-mar-2003 rev1.5 added ert-tx3927-018. added descriptions to the document changes table. 19-july-2006 rev1.6 added ert-tx3927-019. modified some references to the related documents. deleted the document changes table. this specification update will be incorporated into the next revision of the documents. product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf related documents: tx39 family TMPR3927 databook (2003): doc. no = bde0016a tx39/h2 processor core architecture (2000): doc. no = 44124d-9908 - 1 - 4 .com u datasheet
tx3927 restrictions on product use the information contained herein is subject to change without notice. toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system , and to avoid situations in which a malfunction or failure of such toshiba products could cause lo ss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba produc ts specifications. also, please keep in mind the pr ecautions and conditions set fort h in the ?handling guide for semiconductor device s,? or ?toshiba semiconduc tor reliability handbook? etc.. the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, offi ce equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products list ed in this document shall be made at the customer?s own risk. the information contained herein is presented only as a guide for the applic ations of our products. no responsibility is assumed by toshiba for any infri ngements of patents or other rights of the third parties which may result from its use. no license is granted by implicatio n or otherwise under any patent or patent rights of toshiba or others. the products described in this document may incl ude products subject to the foreign exchange and foreign trade laws. the products described in this document contain components made in the united states and subject to export control of the u.s. authorities. dive rsion contrary to the u.s. law is prohibited. if you have any technical questions regarding this document, contact us at: toshiba corporation semiconductor company consumer system lsi design department 580-1, horikawa-cho, saiwai-ku, kawasaki, 212-8520, japan tel +81 -44 -548 -2222 fax +81 -44 -548 -8320 - 2 - 4 .com u datasheet tx3927 ert-tx3927-001 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: after opening moisture-proof packing effective usage period after opening moisture-proof packing store the devices in a cool, dr y area at a temperature of 30 c or less and a humidity of 60% or less. be sure to solder the devices within 48 hours after opening moisture-proof packing. if more than 48 hours has elapsed after opening moisture-proof packing, bake the devices at 125 c for more than 20 hours before soldering them. after baking, store the devices in a cool, dry area at a temperature of 30 c or less and a humidity of 60% or less and be sure to solder the devices within 48 hours. ert-tx3927-002 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: results of electrostatic discharge testing results of electrostatic discharge testing the following table shows the results of electrostatic discharge testing that was performed on this device. when handling individual devices (which are yet to be mounted on a printed circuit board), be sure that the environment is protected against electrostatic electricity. for more information, refe r to the ?general safety precautions a nd usage considerations? section of the databook. standard pins rated voltage rxd[1:0], cts[1:0] 200 v machine model (mm) (eiaj standard) other pins 250 v or more human body model (hbm) (mil standard) all pins 2000 v or more - 3 - 4 .com u datasheet tx3927 ert-tx3927-003 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf note: this is already mentioned in the 2001 edition of the databook (doc.no = 44150d-0111). condition: using the tlb recommended operating supply voltage conditions the following table shows the recommended operating supply voltage conditions for the TMPR3927f/af/bf/cf. keep in mind that the v dd2 rating is different, depending on whether the tlb is on or off. when designing products that include this device, ensure that the recommended operating conditions for the device are always adhered to. parameter symbol condition min max unit i/o v dds 3.0 3.6 v tlb off 2.3 2.7 supply voltage internal logic v dd2 tlb on 2.4 2.7 v - 4 - 4 .com u datasheet tx3927 ert-tx3927-004 product types: TMPR3927f, TMPR3927af, (TMPR3927bf, TMPR3927cf) note: although this problem has been fi xed in the TMPR3927bf/cf, there are some usage limitations. condition: using the pci controller in target mode outline under particular conditions, the pci controller in the tx3927 may assert the stop* signal unnecessarily when the pci bus is idle. symptoms as shown in figure 1 below, the pci controller in the tx3927 may, under particular conditions, assert the stop* signal unnecessarily exactly when the pci bus is idle. the external pci master may be affected by this stop* signal. conditions pciclk frame* irdy* trdy* devsel* stop* normal case a. external pci master tx3927 unnecessary stop* signal * * * * * * figure 1 unnecessary assertion of the stop * signal when the tx3927 pci controller is operating in target mode and an external pci master is bursting to the tx3927, the tx3927 pci controller asserts the stop* signal unnecessarily when the completion of the burst cycle (a in the above figure) coincides with particular conditions of the tx3927. there are the following three conditions: - 5 - 4 .com u datasheet tx3927 1) when all of the following co nditions a) to c) are true: a) bit 3, or the ofifo 8-clock rule enable (of8e) bit, in the target control (tc) register (at 0xfffe_d090) of the pci controller is cleared. b) the current burst cycle is a read. c) the ofifo becomes empty immediately before point a. in the above figure. 2) when all of the following co nditions a) to c) are true: a) bit 4, or the ififo 8-clock rule enable (if8e) bit, in the target control (tc) register of the pci controller is cleared. b) the current burst cycle is a write. c) the ififo becomes full immediately before point a. in the above figure. 3) when all of the following co nditions a) to c) are true: a) bit 11, or the pci snoop (psbp) bit, in the chip configuration (ccfg) register at 0xfffe_e000 is cleared. b) the current burst cycle is a write. c) the cpu core requests bus mastership at point a. in the above figure while another bus master on an internal bus is executing a bus cycle. workarounds burst reads and burst writes require separate workarounds. if both burst reads and burst writes are performed, use both of the following workarounds. 1) when the burst cycle is a read set the of8e bit in the target control (tc) register of the pci controller. 2) when the burst cycle is a write a) set the if8e bit in the target contro l (tc) register of the pci controller. b) set the psnp bit in the chip configuration (ccfg) register. in this case, however, it is prohibited to use the data cache in write-back mode. status this problem has been fixed in the TMPR3927bf as follows. 1) it is possible to clear the psnp bit in the chip c onfiguration register so as to use the data cache in write-back mode. 2) there is still a usage limitation that the of8e and if8e bits in the target control register of the pci controller must be set when the pci controller is used in target mode. - 6 - 4 .com u datasheet tx3927 ert-tx3927-005 product types: TMPR3927f, TMPR3927af condition: assertion of the reset signal during operation outline if the reset signal is asserted under particular conditions, the sdclk, sysclk and pciclk outputs may assume the hi-z state. symptoms if the reset signal is asserted under particular conditions, the sdclk, sysclk and pciclk outputs may assume the hi-z state. consequently, devices that operate with these clocks may be affected. for example, when the sdclk output enters the hi-z st ate, a constraint for the sdram clock is violated. as a result, the sdram might tran sition to an unexpected state. conditions during a reset sequence, the states of addr[4], [5] and [18] are used to determine whether or not to enable the sdclk, sysclk and pciclk outputs. ? sdclk: when addr[4] is 1 during boot-up, sdclk is generated. when 0, it is put in the hi-z state. ? sysclk: when addr[5] is 1 during boot-up, sysclk is generated. when 0, it is put in the hi-z state. ? pciclk: when addr[18] is 1 during boot-up, pciclk is generated. when 0, it is put in the hi-z state. since each addr pin has an internal pull-up re sistor, these clocks are usually generated. however, if the above addr pins are driven low wh ile the reset signal is asserted, sdclk, sysclk, and pciclk assume the hi-z state until these addr pins are pulled high by the pull-up resistor. workarounds when the reset* input is applied to the tx3927, all devices that use the sdclk, sysclk or pciclk output should be reset. with regard to sdram, rem ove the sdram power supply to bring it back to the initial state (power-on state) because it has no reset pin. status this problem has been fixed in the TMPR3927bf as follows. 1) in the reset state, the sdclk and syclk outputs remain enabled. the boot-up configurations of sdclk and syclk by the addr[4] and addr[5] pins were deleted. 2) the sdclk and sysclk outputs can still be disabled after boot-up via the pin configuration (pcfg) register at 0xfffe_e008. these pins will assume the hi-z state when disabled. 3) the specification pertaining to pciclk has not been modified. - 7 - 4 .com u datasheet tx3927 ert-tx3927-006 product types: TMPR3927f, TMPR3927af note: this problem occurs with the tx 39/h2 core whose prid is 0x0000_2240. condition: using the tlb outline the operation of a branch-likely instruction changes under particular conditions when the tlb is used. symptoms the operation of a branch-likely instruction changes under particular conditions when the tlb is used. conditions the branch-likely instruction nullifies the instruction in its delay slot when the branch condition is false. however, under the conditions described below, the instruction in the delay slot is executed, changing the program behavior. the conditions that cause th is problem are as follows: 1) the tlb is used for the instruction. 2) the last two instructions on the page boundary are a branch-likely instruction and an instruction for its delay slot. 3) an int or dint exception occurs on the instruction in the delay slot. (note 1) 4) the above branch condition is false. 5) the instruction following the delay slot causes an itlb miss. (note 2) only when all these conditions are true at the same time , the address of the delay slot is stored into the epc (or depc) register instead of the address of the bran ch-likely instruction, and bd (or dbd) bit in the cause (or debug) register is not set. therefore, after returning from the exception handler, the instruction in the delay slot is executed instead of being nullified. note 1: both nmi and buserr cause the same problem. however, nmi is an imprecise exception, and the return from an exception is not origina lly guaranteed. since buserr is a fatal error, it is impossible to reco ver from this exception. note 2: the tx39/h2 processor core has a two-en try instruction tlb (itlb) like a cache memory. an itlb miss does not cause a tlb exception, si nce it is refilled from the actual tlb by hardware. - 8 - 4 .com u datasheet tx3927 workarounds include the following code in the interrupt handler. ------------------------------------------------------------------------------------------------------------------------------------ // if the epc (or depc) register points to the end of a page and the preceding instruction is a branch-likely // instruction, modify the epc (or depc) register. tx3927 example procedure example of a patch procedure rela ted to the branch-likely operation #define badaddr_off 0xffc mfc0 a0, epc_save_area // save epc -> a0 (note) li a1, badaddr_off and a2, a0, a1 bne a2, a1, patch_exit nop lw a1, -4(a0) li a2, 0xf0000000 li a3, 0x50000000 and a2, a1, a2 beq a2, a3, err_intr nop li a2, 0xfc0e0000 li a3, 0x04020000 and a2, a1, a2 beq a2, a3, err_intr nop li a2, 0xf3fe0000 // li a2, 0xf01e0000 li a3, 0x41020000 // li 0x40020000 and a2, a1, a2 beq a2, a3, err_intr nop j patch_exit nop err_intr: addiu a0, a0, -4 sw a0, epc_save_area patch_exit: note: modify the address of epc_save_area and the register number, depending on the os used. - 10 - 4 .com u datasheet tx3927 ert-tx3927-007 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: using the pci controller outline under particular conditions, the processing of a bus e rror exception that occurs during a pci configuration read doesn?t work correctly. bus error exceptions due to other causes are processed properly. symptom when the following conditions are true, the processing of a bus error exception doesn?t work properly. conditions this error occurs when all of the following conditions are true: 1) timeout error is enabled. that is, the toe bit of the chip configuration (ccfg) register is set to 1. 2) a pci configuration read is ex ecuted in direct mode. that is, it is executed via the initiator configuration data register (icdr) at 0xfffe_d13c and the initiator configuration address register (icar) at 0xfffe_d138. a pci configuration write causes no error. 3) a bus error exception occurs due to a g-bus timeout. it occurs under the following conditions: a) the target pci device repeats the ?retry? because its initialization is incomplete, etc. (i.e., repeats the ?retry? via the stop* signal without asserting the tready signal) b) the pci bus is deadlocked because the tx3927 and target pci device repeat the ?retry? with each other. (this might occur in systems in whic h the tx3927 is configured to operate in both target and initiator modes. see page 12-84 of the tx3927 databook.) c) the tx3927 couldn?t receive an acknowledge from the target pci device within 512 g-bus clock cycles because the pci bus traffic is crowded. workarounds there are two workarounds for this problem. use either one of them. 1) execute a pci configuration read in indirect mode. the indirect mode can be executed by using the following registers: ? initiator indirect address regi ster (ipciaddr) at 0xfffe_d150 ? initiator indirect data register (ipcidat) at 0xfffe_d154 ? initiator indirect command/byte enable register (ipcicbe) at 0xfffe_d158 ? initiator status register (istat) at 0xfffe_d044 - 11 - 4 .com u datasheet tx3927 in direct mode, a pci configuration read cycle is executed when the cpu reads the icdr register. the tx3927 local bus cycle doesn?t finish until the pci bus cycle finishes. on the other hand, in indirect mode, pci bus cycles start asynchronously to the tx3927 local bus when the cpu writes an address and command to the ipciaddr and ip ciibe registers. the result of a pci configuration read is loaded into the ipcidata register. the completion of a pci configuration read can be checked by polling the istat register. (an interrupt can also be sent via the initiator interr upt mask (iim) register at 0xfffe_d048.) that is, in this mode, the local bus cycle finishes without waiting for a reply from the target pci device. therefore, a bus timeout error doesn?t occur. note that the address and command are loaded into the ipciaddr and ipcicbe registers. the contents of the ipciaddr register will be pla ced on the pciad bus directly during the address phase, and the contents of the icmd and ibe fields in the ipcicbe register will be executed as a pci command and byte enables. refer to the following example code for indirect mode. keep in mind that this is just a sample code. toshiba does not warrant its use in your system. you should always verify its operation in your system. 2) disable timeout errors; that is, cl ear the toe bit of the ccfg register. in this case, the bus timeout error will never occur. however, there is a possibility that the tx3927 will be deadlocked when the local bus is waiting for an acknowledge from the target device. for instance, repeated retries by the target pci device will cause a deadlock. to avoid a deadlock, a system should be designed to assert a reset when it detects system failures such as a bus deadlock by using the wdt (watchdog timer), etc. example code the following is an example code in which pci conf iguration cycles are executed in indirect mode. this code is just an example. if an operating system is used, a routine that is called by an interrupt or rtos might modify the istat, ipciaddr, ipcidata and ip cicbe registers. when you use this routine, exclusive control may be required so that the c ontents of these registers will not be altered. ------------------------------------------------------------------------------------------------------------------------------------ /* this sample code is suitable fo r type 0 configuration cycle */ #define waittime 0x1000 void dummyloop(void){ int i; for( i=0; i< waittime;i++); } unsigned int indirect_config_read( unsigned int dev, unsigned int func, unsigned int reg) { /* dev : target device number : 0x00 -- 0x14( ad[11] -- ad[31] ) */ /* func : target device function number : 0x0 -- 0x7 */ - 12 - 4 .com u datasheet tx3927 /* reg : terget device configration space address offset : 0x00 -- 0x3f */ unsigned int address; /* ad[31:0] during the address phase */ unsigned int read_data; /* the value of configration read data */ /* istat register idicc bit == 1 , write clear */ if( *(unsigned int *)(0xfffed044) & 0x00001000 ){ *(unsigned int *)(0xfffed044) = 0x00001000; } /* make address value */ address = 0x00000000 |((0x1) << (11 + (dev & 0x1f)) )|((func & 0x7) << 8) | ((reg & 0x3f)<<2); *(unsigned int *)(0xfffed150) = address; /* execute indirect configration read */ *(unsigned int *)(0xfffed158) = 0x000000a0; /* status polling configration access */ while(1){ if( *(unsigned int *)(0xfffed044) & 0x00001000 ){ /* istat register idicc bit == 1 , indirect initiator command terminates */ break; } dummyloop(); } /* read cofigration register value from internal register */ read_data = *(unsigned int *)(0xfffed154); /* clear idicc bit(istat register's all bit are r/wc) */ *(unsigned int *)(0xfffed044) = 0x00001000; return read_data; } void indirect_config_wirte(unsigned int dev, unsi gned int func, unsigned int reg, unsigned int data) { unsigned int address; /* ad[31:0] during the address phase */ /* istat register idicc bit == 1 , write clear */ if( *(unsigned int *)(0xfffed044) & 0x00001000 ){ *(unsigned int *)(0xfffed044) = 0x00001000; } /* make address value */ - 13 - 4 .com u datasheet tx3927 address = 0x00000000 |((0x1) << (11 + (dev & 0x1f)))|((func&0x7) << 8) | ((reg & 0x3f)<<2); *(unsigned int *)(0xfffed150) = address; /* write value set internal register */ *(unsigned int *)(0xfffed154) = data; /* execute indirect configration write */ *(unsigned int *)(0xfffed158) = 0x000000b0; /* status polling configration access */ while(1){ if( *(unsigned int *)(0xfffed044) & 0x00001000 ){ /* istat register idicc bit == 1 , indirect initiator command terminates */ break; } dummyloop(); } /* clear idicc bit(istat register's all bit are r/wc) */ *(unsigned int *)(0xfffed044) = 0x00001000; } ------------------------------------------------------------------------------------------------------------------------------------ - 14 - 4 .com u datasheet tx3927 ert-tx3927-008 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: using the rom controller in half-speed mode outline when a memory location is accessed via a rom contro ller channel conf igured for half-speed mode, the assertions of addr, ace*, ce*, oe* and be* are delayed by t sysh /2 (i.e., a half of the reference clock for half-speed mode). since these signals are deassert ed as usual, the active periods of these signals become t sysh /2 shorter than the usual. no problem occurs when all channels are programmed in full-speed mode. symptom under particular conditions, the assertions of addr, ace*, ce*, oe* and be* are delayed by t sysh /2 (i.e., a half of the reference clock for half-speed mode) when the tx3927 rom controller accesses the area mapped to a half-speed channel. consequently, the active periods of these signals become t sysh /2 shorter than the usual. conditions if bit 4, or the half-speed bus (rhs) bit of the ro m channel control registers for one or more channels (rccr0-7 at 0xfffe_9000-901c) is set, this problem occurs when the following conditions become true simultaneously: 1) addr changes at the same time as the assert ion of the gbstart* on the tx3927 internal bus (g-bus). this occurs in one of the following situations: a) the dmac starts a bus cycle. b) the pcic starts a bus cycle. c) the cpu starts a bus cycle immediately af ter ghpggnt*, which is one of the bus grant signals for the g-bus, is deasserted. ghpggnt* will be deasserted when the ghpgreq* or ghaveit* is deasserted. ghpgreq* is a g-bus request without data cache snooping. ghaveit* is a signal to confirm g-bus ownership. that is, when the dmac and pcic are programmed to use ghpgreq* as a bus request signal and the cpu starts a bus cycle immediately after it has granted the bus to the dmac or pcic. 2) the above bus cycle is an access to the area mapped to a half-speed channel. 3) the beginning of the bus cycle is not aligned with the phase of the reference clock for half-speed mode. that is, when the bus cycle starts at the falling edge of the reference clock. - 15 - 4 .com u datasheet tx3927 under these conditions, addr, ace*, ce*, oe* and be* are delayed by t sysh /2 (i.e., a half of the reference clock for half-sspeed mode ). since these signals are deasserted as usual, their active periods become t sysh /2 shorter than the usual. note: ghpggnt * , ghpgreq * and ghaveit * are internal signals of the tx3927. workarounds there are the following three workarounds for this problem. use the one best suited for your application. 1) use gsreq* instead of ghpgreq* as a g-bus request signal for the pcic and dmac. in addition, program the pcic and dmac not to access any area mapped to the half-speed channels. for this workaround, it is nece ssary to program registers as follows. a) set bit 11, or the pci snoop (psnp) bit, of the chip configuration (ccfg) register (at 0xfffe_e000). b) set bit 7, or the snoop (snop) bit, of the channel control register (ccrn) (at 0xfffe_b018, 0xfffe_b038, 0xfffe_b058 or 0xfffe_b078). c) clear bit 13, or the write-back mode on (wbo n) bit, of the config register (cp0: r3) to configure the cache for write-through (non-write-allocate) mode. this is necessary because data cache snooping programmed by a) and b) above can not be used in write-back mode. d) configure the dmac not to access any area mapped to the half-speed channels. e) configure the pcic not to access any area mapped to the half-speed channels. keep in mind that this workaround allows only write-back mode for the data cache. note: gsreq * is a bus request with data cache snooping. it is an internal signal of the tx3927. 2) when more than one rom controller channel is used in half-speed mode, design a system, based on the ac specification shown on the following page. 3) use the rom controller only in full-speed mode. - 16 - 4 .com u datasheet tx3927 sdramc and romc ac characteristics difference the output delay is defined separately for full-speed (td) and half-speed (tdh) modes. in half-speed mode, the specs of addr, ace*, ce*, oe* and be* differ from those of the other signals. (tc = 0 to 70c, v dd s = 3.3 v 0.3 v, v dd 2 = 2.5 v 0.2 v, v ss = 0 v, cl = 50 pf) parameter signals description min max unit t sys sysclk/sdclk[4:0] cycle time (full-speed bus mode) 15 ns t sysh sysclk cycle time (half-speed bus mode) 30 ns t sysm sysclk/sdclk[4:0] min high/low level 5 ns t sysmh sysclk min half-speed high/low level 12 ns t d (1) output delay (full-speed bus mode) 7 ns t dh (3) output delay (half-speed bus mode) 7 ns t dh (4) output delay (half-speed bus mode) t sysh /2 + 7 ns t oh (1) output hold 1 ns t su (2) input setup 7 ns t ih (2) input hold 0 ns t daz data[31:0], ack * data active to hi-z 7 ns t dza data[31:0], ack * data hi-z to active 1 ns (1) ack * , data[31:0], ce[7:0] * , oe * , ace* , swe * , bwe[3:0] * , addr[19:2], dmaack[3:0], dmadone * , pio[15:0], timer[1:0] (2) ack * , data[31 0], nmi * , int[5:0], dmareq[3:0], dmadone * , pio[15:0] (3) ack * , data[31:0], bwe[3:0] * , swe * , dmaack[3:0], dmadone * , pio[15:0], timer[1:0] (4) ce[7:0] * , be* [3:0], oe * , ace * , addr[19:2] timing diagram (sdramc and romc signals) sysclk td, tdh tsysm, tsysmh tsym, tsysh tsysm, tsysmh toh tdaz tdza output tsu tih sysclk input - 17 - 4 .com u datasheet tx3927 ert-tx3927-009 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf note: this problem occurs with the tx 39/h2 cores whose prid is 0x0000_2240, 0x0000_2241 or 0x0000_2242. condition: using data cache snooping in doze mode outline in doze mode, even if an external master owns the bus and performs data cache snooping, the corresponding data in the da ta cache is not invalidated. the tx3927 enters doze mode when the doze bit (bit 9) of the config register (cp0: r3) is set to 1. in doze mode, the bus can be released in response to a bu s request signal. if the snoop signal is sampled as asserted at the rising edge of a cl ock while an external master owns th e bus, the cache line containing the data whose address is equal to that of the address bus is invalidated. however, due to a bug, even if data cache snooping is performed in doze mode, the data in the data cache is not invalidated. symptom after the tx3927 returns from doze mode , correct data may not be read. conditions this problem occurs when data cache snooping is used in doze mode. in other modes, data cache snooping works normally. workarounds there are the following three workarounds. us e the one best suited for your application. 1) don?t use data cache snooping. 2) don?t use doze mode when data cache snooping is used. however, if udeos/r39 is used, when execution passes to an idle task, the doze bit (bit 9) of the config register (cp0: r3) is automatically set to 1 by the os. therefore, the source file (kidle.c) of the os needs to be modified so as not to use doze mode. however, this workaround cannot be used for a library package. prepare a lowest-pri ority task. (refer to ?workaroud example for udeos/r39.?) 3) when data cache snooping is used in doze mode, invalidate the cache when the doze mode exited. notes on doze mode by os 1 udeos/r39 doze is used. 2 vxworks no problem (doze is not used.) 3 wince refer to item 3 below. 4 linux no problem (doze is not used.) - 18 - 4 .com u datasheet tx3927 1) udeos/r39 in v3.3.0 or earlier versions of udeos/r39, when execution passes to an idle task, the doze bit (bit 9) of the config register (cp0: r3) is automatica lly set to 1 by the os. therefore, the source file (kidle.c) of the os needs to be modified so as not to use doze mode. however, this workaround cannot be used for a library packag e. prepare a lowest-priority task. also, when you use doze mode, avoid a problem according to the workaround. 2) vxworks vxworks for the tx3927 uses the vxworks kernel of tornado 2.0/r3000, and only the cache library is replaced for tx39/h2 cores. that is, all functions are compatible with r3000 except the cache library. for this reason, do ze mode is not supported by the os , but you can use it on your own responsibility. when you use doze mode, av oid a problem according to the workaround. 3) wince ask your si vender for details of this matter. when you use doze mode in your system, avoid a problem according to the workaround. 4) linux linux (monta vista linux) of montavista software, inc. does not use doze mode in its kernel. when you use doze mode, avoid a problem according to the workaround. workaround example for udeos/r39 the following example for udeos/r39 uses workdaround 2) described above. 1. changing the source file of the os in udeos/r39 v3.3.0 or earlier, when execution passe s to an idle task, the doze bit of the config register is set in ./src/kidle.c. (kidle.c) before modification task tr_eidl(void) { for(;;){ #if defined(tr_knl_log) || defined(tr_mtd_log) /* record idle log */ tr_writelog(tr_log_idl, 0, (id)0, (id)0, 0); #endif /* power-saving mode */ tr_lowpower(); } } edit the source code as follows so as not to enter doze mode and rebuild a kernel. - 19 - 4 .com u datasheet tx3927 (kidle.c) after modification task tr_eidl(void) { for(;;); } the code for recording an idle log has been deleted so that buffers will not be filled up with an idle log. the kernel can still recognize when th e process changes into the idle state. 2. not changing the source file of the os create a task with a priority lower than the lowest-priority task currently used in the application. identify this task in a configuration macro. cre_tsk(id, exinf, ta_hlng | ta_start, task, pri, stk) the content of the task is as follows. task task( ) { for(;;); } kidle.c is not contained in the library package. thus, workaround 1, ?changing the source file of the os,?cannot be used. use workaround 2 instead. - 20 - 4 .com u datasheet tx3927 ert-tx3927-010 product types: TMPR3927f, TMPR3927af, TMPR3927bf note: this problem occurs in the tx39/ h2 cores whose prid is 0x0000_2240 or 0x0000_2241. condition: using write-back mode outline in write-back mode, the internal bus (g-bus) and external buses such as the sdram bus may be locked. this problem may occur when the data cache is flushed by the cache instruction while the dmac or pcic owns the g-bus through a non-snooping-capable bus request signal. due to this bug, even if the toe bit (bit 14) of the chip configuration (ccfg) re gister is set and a timeout for bus errors is enabled, a bus error does not occur. in addition, when the watchdog timer of the tx3927 is used, although a reset is effective for the tx3927, whether or not it is effective for the entire system depends on your system design. if the reset is not effective for the entire system, you must turn off the power supply to your system. symptom the g-bus and external buses such as the sdram bus may be locked. conditions this error may occur if both of the following conditions are true: 1) the write-back mode is used. 2) the cache instruction is execu ted to flush the data cache while an external master owns the g-bus. the cache instruction with the operation field (bits 20:16) of 0x01, 0x15 or 0x19 flushes the data cache. this problem doesn?t occur during a burst write operati on that is triggered for a cache replacement due to a cache miss. workarounds there are the following two workarounds for this problem. you can avoid this problem by using either one of them. 1) use write-through mode. 2) when using write-back mode, don?t use the cache instruction for flushing the data cache while an external master owns the g-bus. status this problem has been fixed in the TMPR3927cf. workaround examples here are examples of workaround 2 described above. in these examples, the cache is flushed without using the cache instruction. - 21 - 4 .com u datasheet tx3927 < example 1 > 0x8000_0000?0x9fff_ffff and 0xa000_0000?0xbfff_ffff in the virtua l address space are mapped to the same range in the physical a ddress space (0x0000_ 0000?0x1fff_ffff). 0x8000_0000?0x9fff_ffff is a cached area whereas 0xa000_ 0000?0xbfff_ffff is an uncached area. consequently, reading data from a cached area and writ ing that data to an uncached area whose physical address is the same as the read address has an effect equivalent to flushing the data cache with the cache instruction. 0x0000_0000 0xffff_ffff 0xc000_0000 0xa000_0000 0x8000_0000 0x2000_0000 0x0000_0000 0xffff_ffff kseg0 (cached) kseg1 (uncached) virtual address space physical address space for example, if the data address that is the target of cache flushing is 0x8000_0000, perform the following steps: 1) read out data from 0x8000_0000. because 0x8000_0 000?0x9fff_ffff is a cached area, a read request is first issued to the data cache. thus, when address 0x 8000_0000 hits in the data cache, data is read from it. in the case of a cache miss, data is read from main memory (physical addr ess 0x0000_0000). 2) write the data that was read in step 1) to 0xa000_0000. because 0xa000_00 00?0xbfff_ffff is an uncached area, data is always written to main memory (physical address 0x0000_0000). 3) invalidate the data cache line containing data whos e address is the same as that of step 1). this can be done with the cache instruction with the op field (bits 20:16) of 0x11. in other words, when a read hits in the data cache, cache flushing (a read from the cache and a write to main memory) is done by the above operation. however, in the case of a cache miss, a read and a wr ite is done to same memory address; so the above operation is a waste of time. < example 2 > when there is an unused cached data area of more than four kbytes, the entire data cache area can be flushed by reading the area of more than four kbytes in sequence (since cache replacements occur due to cache misses). - 22 - 4 .com u datasheet tx3927 ert-tx3927-011 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: using the pci controller in target mode outline under specific conditions, a pci read accesses the address following the one that was written immediately before the read instead of the specified read address. symptom under specific conditions, when the tx3927 pcic is r ead as the target, the read access may be performed to a wrong address. conditions under these setup conditions, this problem may occur when pci accesses occur in the following order. < setup > 1) when data in the ofifo is cached after completion of a pci transaction. that is, when the ofcad bit (bit [19]) of the targ et control (tc) register is cleared to 0. the default value of this bit is 0. 2) when read streaming from the local memory to the ofifo is enabled for a pci read request. that is, when the ofpfo bit (bit [ 12]) of the tc register is cleared to 0. the default value of this bit is 0. < the order of pci accesses that causes this problem > 1) the pci device reads from the tx3927 local memory. the data-in to the ofifo is so late that the pci read cycle ends with a retry. (the tx3927 is reading from the local memory to the ofifo.) 2) the pci device writes to the tx3927 local memory. actually, the pci transaction is finished when data is written to the ififo. the write operation from the ififo to the main memory is made to wait until the read from the local memory to the ofifo is completed. 3) the pci device reads from the tx3927 local memory again. because there is data in the ofifo this time, data is returned and the pci transaction is finished. 4) the pcic completes the write operation from the ififo to the local memory before step 3 is finished, or the pcic is still executing a write to the local memory when step 3 is finished. 5) the pci device reads data from a location of the tx3927 local memory that follows the address of the previous read. - 23 - 4 .com u datasheet tx3927 when the timing of step 4 occurs, the address of the local bus cycle being executed by the pcic is latched into the address pointer of the local ofifo bus. because step 5 is an access to the address that follows the previous address, when the pcic is programmed for the tx3927 ert-tx3927-012 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: using the ?never time out? feature of the pci controller outline the pci bus may be locked when the never time out feature of the pcic is enabled and the tbl_ofifo field (bits [7:4]) of the target burst leng th (tbl) register is programmed to 16 dwords. the never time out feature is enabled when the ofnte bit (bit [18]), of16e bit (bit [5]) and of8e bit (bit [3]) of the target control (tc) register are all se t to 1.the tbl_ofifo field (bits [7:4]) of the tbl register is programmed to 16 dwords when it is set to 01xx or 1x1x. symptom if the never time out feature of the pcic is enabled, the pci bus may be locked when the tx3927 pcic is accessed as a target under particular conditions. conditions under these setup conditions, this problem may occur as follows: < setup > 1) when the never time out feature is enabled. that is, when bit [18] of the tc register is set to1. the default is 0. 2) when bits [7:4] of the tbl register are set to 01xx or 1x1x. < the process that c auses this problem > the following process causes this problem when an ex ternal bus master inserts a wait state by deasserting irdy at the timing of the 16th dword when it is reading 16 dwords from the tx3927. 1) because the transaction finishes at the next dword, the tx3927 considers that the transaction will finish at the next clock when the 15 th dword is read, and stops there. 2) irdy is set low again, and the external pci bus master keeps waiting for the next data. because the never time out feature is enabled, the tx3927 can't finish the transaction by asserting the stop* signal. also, since bits [7:4] of the tbl register are progr ammed to 16 dwords, which is the same size as the fifo, the next data can't be put into the ofifo becaus e the final data (1 dword) re mains left in the ofifo. thus the output level (the number of words) for the pci bus of the ofifo is not satisfied. because the transaction isn't finished and the pci bus ma ster doesn't release the bus, the pci bus is locked. - 25 - 4 .com u datasheet tx3927 workarounds there are the following two workarounds for this problem. you can avoid this problem by using either one of them. 1) disable the never time out feature. in other words, clear bit [18] of the tc register to 0. (default = 0) 2) set bits [7:4] of the tbl register to a value other than 01xx and 1x1x. notes on the use of an os refer to the ?notes on the use of an os for ert-tx3927-011 to ert-tx3927-014? shown in ert-tx3927-014. - 26 - 4 .com u datasheet tx3927 ert-tx3927-013 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: using the pci controller in target mode outline the location of the pcic address space is specified in the target memory base address size (mbas) and target i/o base address size (iobas) registers. the la st four dwords of this sp ace are reserved for the pcic. when the ofard bit (bit [8]) or the ifard bit (b it [7]) of the target control (tc) register is cleared to 0, the specification of the tx3927 is as follows: ?the pcic wi ll issue a target-abort if an attempt is made by an external pci bus master to access ad dresses outside the defined pci address space or to access the reserved area.? however, the pcic actually operates as follows: ? burst access the first three dwords can be accessed. when the last dword is accessed, the pcic issues a target-abort. ? single access the first one dword can be accessed normally. the subsequent single access causes a master-abort instead of a target-abort. symptom when the reserved area of the pcic is accesse d, the pcic does not operate as specified. conditions this problem occurs under the following conditions. 1) when the ofifo address range checking is enabled. that is, when bit [8] of the tc register is cleared to 0. the default is 0. 2) when the ififo address range checking is enabled. that is, when bit [7] of the tc register is cleared to 0. the default is 0. workaround don?t access the reserved area of the pcic. notes on the use of an os refer to the ?notes on the use of an os for ert-tx3927-011 to ert-tx3927-014? shown in ert-tx3927-014. - 27 - 4 .com u datasheet tx3927 ert-tx3927-014 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: using the pci controller in initiator mode outline/symptom when a three-byte data access is done over the pci bus in initiator mode, irdy is negated automatically at the fifth clock when the value of cbe becomes 0001b. therefore, the following problems occur if trdy isn?t asserted by this time: ? reads and writes aren?t performed correctly. ? the pci target device can?t negate trdy. conditions this error may occur if both of the following conditions are true: 1) when a three-byte data access is done over the pci bus in initiator mode. there are two cases in which a th ree-byte data access is performed over the pci bus in initiator mode. this error occurs in both of the following cases: a) the cpu performs a three-byte access in direct mode. b) the cpu performs a three-byte access in indirect mode. 2) when the value of cbe is 0001b. workaround don?t perform a three-byte data access over the pci bus in initiator mode. notes on the use of an os for er t-tx3927-011 to ert-tx3927-014 the following paragraphs describe the influences that the problems discussed in ert-tx3927-011 to ert-tx3927-014 have on the os. when you use an os except the following, drivers, middleware and so on, verify such software because it has the possibility of causing problems. 1) udeos/r39 udeos/r39 doesn?t control the pcic. when you use the pcic in your system, avoid a problem according to the workaround. 2) vxworks ? ert-tx3927-011, ert-tx3927-012 if you use the bsp for the jmr-tx3927 from wind river without modification, this problem does not occur. if you change its settings, be sure to avoid a problem according to the above workaround. additionally, earlier releas es of bsps provided by toshiba as samples may also be affected by this problem. if you use a toshiba-provided bsp, please check the values of the tc and tbl registers. - 28 - 4 .com u datasheet tx3927 ? ert-tx3927-013 the value of the tc register satisfies the cond itions for an occurrence of this problem. be careful not to access the reserved area of the pcic. ? ert-tx3927-014 no problem occurs when you use the pci drivers (tc35815, rtl8029 and intel 82557/8/9) from toshiba for jmr-tx3927 +vxworks. if you include a driver other than those, avoid a problem according to the workaround. 3) wince wince has the possibility of causing problems discussed in ert-tx3927-11 to ert-tx3927-14. ask your si vender for details of this matter. 4) linux (monta vista linux) no problem occurs when the bsp for jmr-tx3927 from monta vista software, inc. is used as-is. when you build your system, avoid a problem according to the workaround. - 29 - 4 .com u datasheet tx3927 ert-tx3927-015 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf note: this problem occurs with the tx 39/h2 cores whose prid is 0x0000_2240, 0x0000_2241 or 0x0000_2242. condition: using the the bus timeout error function outline the tx3927 generates a bus error if the internal bus cycle has timed out when the toe bit (bit [14]) of the chip configuration (ccfg) register is set to1. if a bus error occurs, the cpu core may hang immediately due to a bag. symptom when the bus error occurs, the cp u core may hang immediately. conditions this error may occur if all of the following conditions are true: 1) the bus timeout error feature is enabled. that is, when the toe bit of the ccfg register is set to1. the default is 0. 2) the bus error exception is vectored to a cacheable area. that is, wh en the bev bit (b it [22]) of the status register is cleared to 0. the default is 1. 3) no read operation occurs on th e internal bus before all four lines of the write buffer are filled with write data after a bus error. 4) the cpu core requires a write operation when all f our lines of the write buffer are filled with write data. workarounds there are the following two workarounds. you can avoid this probl em by using either one of them. 1) load from the cache area at the top of the exception handler. refer to example 1 for a workaround program. this workaround must be executed before the first store operation after a bus error. this workaround is not effective if the data cache is disabled. this workaround is not effective if the load address is in the cache when loading from the cache area, because the read operation does not occur over the internal bus. to avoid this, execute cache-invalidate for th e load address before a load operation. if the cache is programmed for write-back mode, th e necessary data may disappear as a result of cache-invalidate. to avoid this, the data in a cache line that is hit by a load address must be read-only data. (in the case of example 1, this is four words at 0x80000000?-0x8000000c.) - 30 - 4 .com u datasheet tx3927 < example 1 > 0x80000080 lui r10, 0x8000 84 ori r10, r10, 0x0000 ;r10 <- 0x80000000(cache area) 88 cache 17, 0(r10) ;cache line that hits in r10 is invalidated. 8c lw r11, 0(r10) ;read from r10 2) execute the instruction fetch from an uncachea ble area at the top of the exception handler. refer to example 2 for a workaround program. this workaround must be executed before the first store operation after a bus error. in example 2, suppose that the exception handler is located after 0x80000090. the program re-jumps to the exception handler after jumping to the uncacheable area. < example 2 > 0x80000080 lui r10, 0xbfc0 ;cache area 84 ori r10, r10, 0x1000 88 jr r10 ;jump to uncacheable area 8c nop ;operation of the exception handler 0xbfc01000 lui r11, 0x8000 ;uncacheable area 04 ori r11, r11, 0x0090 08 jr r11 ;jump to the exception handler 0c nop notes on the use of an os 1) udeos/r39 part of the source code of the exception vector is provided. if this problem occurs in your system, avoid it according to the workaround. 2) vxworks the code of the exception vector is set by the vx works kernel. if a bus erro r exception occurs, this problem occurs, depending on whether the exception vector code hits or misses in the cache. to avoid this problem, the exception vector code needs to be modified. contact toshiba if you want to know how to modify the exception vector code. the bus error exception doesn?t occur when the timeout feature is disabled. in the bsp of jmr-tx3927 from wind river systems, inc. or toshiba, the timeout feature is enabled. 3) wince this problem may occur. contact toshiba for details. 4) linux (monta vista linux) part of the source code of the exception vector is provided. if this problem occurs in your system, avoid it according to the workaround. - 31 - 4 .com u datasheet tx3927 ert-tx3927-016 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: using the break f unction of the sio outline when the transmitter sends a break condition in the middle of data, the tx3927 detects only the first framing error, but can't detect the break condition. the tx3927 can detect a break condition normally when it is synchronized with a start bit (the received data remains low after the start bit ). < abnormal operation > status s 1 2 3 4 5 6 7 8 p s sin start flame error ? the receive status remains idle because the star t bit can?t be recognized after a framing error. < normal operation > status s 1 2 3 4 5 6 7 8 p s s 1 2 3 4 5 6 7 8 p s sin start 1st break 2nd break ? the break condition can be detected normally when the received data remains low after the start bit. symptom the tx3927 may not be able to detect a break condition. conditions this problem may occur when the transmitter sends a break condition in the middle of data. workaround when sending a break condition to the tx3927, it must be synchronized with the start bit (the data must remain low after the start bit.). - 32 - 4 .com u datasheet tx3927 notes on doze mode by os 1) udeos/r39 the sio driver is not contained in udeos/r39. if y our application uses the break function of the sio, avoid a problem accord ing to the workaround. 2) vxworks the io driver of vxworks doesn?t support the break function. thus the os driver and routines that use this driver are not affected by this problem. if your application uses the break function of the sio, avoid a problem accord ing to the workaround. 3) wince this problem may occur, depending on your error ha ndling. if the conditions of this problem apply to your system, the tx3927 can?t detect a break condition. handle the break condition as a framing error. 4) linux (monta vista linux) the io driver of monta vista linux doesn?t supp ort the break function. thus the os driver and routines that use this driver are not affected by this problem. if your application uses the break function of the sio, avoid a pr oblem according to the workaround. - 33 - 4 .com u datasheet tx3927 ert-tx3927-017 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: using the tx3927 pcic in satellite mode outline according to the specification, the r/ wl bits in the pci configuration registers of the tx3927 can?t be written by the external pci master. however, these bi ts are written by the pci bus master in some cases. this occurs when the configuration space of the tx39 27 is written by the external pci master while the cpu core of the tx3927 is writing to the internal bus. the data that is written by the pci master is loaded into the register. here is a list of the r/wl bits in the pci configuration registers: ? fbbcp and uspcp bits in the pcis tat register (addr: 0xfffed006) ? cc register (addr: 0xfffed008) ? scc register (addr: 0xfffed009) ? rid register (addr: 0xfffed00b) ? svid register (addr: 0xfffed02c) ? ssvid register (addr: 0xfffed02e) ? ml register (addr: 0xfffed03c) ? mg register (addr: 0xfffed03d) ? ip register (addr: 0xfffed03e) symptom the r/wl bits in the pci configuration registers of the tx3927 may be written by the pci bus master. conditions this error may occur if the following conditions are true at the same time: 1) the external pci master writes to the r/wl bits in a pci configuration register of the tx3927. 2) the cpu core of the tx3927 writes to the internal bus. workaround when the external pci master writes to the r/wl bits of a pci configuration register of the tx3927, it must perform a read-modify-write operation to write the same values as the read ones to the r/wl bits. notes on doze mode by os if your system uses the tx3927 in satellite mode, be careful because this proble m may affect your system. - 34 - 4 .com u datasheet tx3927 ert-tx3927-018 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf condition: using the ?pci broken ma ster checking? feature outline and symptom if you enable the pci broken master checking feature, a working master device may be regarded as a broken master device and detached from the pci bus arbiter. * the broken master checking feat ure of the pci controller identifies a pci master that does not start a bus access even when it has gained bus ma stership. it is treated as broken and excluded from the bus arbitration process. when a given bus master is treated as broken, another pci master might be treated as broken at the same time. conditions (1) the broken master check en able bit is set (bmcen=1). this bit is bit 0 of the pci bus arbiter/parked master control register (pbapmc). the default is 0. (2) there are two pci bus arbiter groups: higher-p riority group and lower-priority group (see the following figure). the assignment of pci bus masters to the bus arbiters is specified in the request trace register (req_trace). (3) when a master device in the higher-priority grou p is detected as broken, a master device in the lower-priority group activates a pci bus request and is given the highest priority in that group. among the lower-priority group, master w has the highest priority upon reset. afterwards, a master which got the pci bus last has the highest priority. (a master with the highest priority is called a parked master.) if all the above conditions become true simultaneously, this problem occurs and the parked master device is detached from the pci bus arbiter. - 35 - 4 .com u datasheet tx3927 lower priority hi g her priorit y master b master c master d master a lower level pci master device 1 pci master device 2 request request grant does not start data transfer within 16 pciclks actually broken regarded as a broken device mistakenly pci controller working master w master y master z master x (parked master) pci bus arbitration priority (an example when a problem occurred) orkarounds orkarounds for this problem: ing feat ure by clearing the bmcen bit of the pbapmc 2) if you need to use the broken master checking feature, then only use the higher-level arbiter tatus no plan to fix this bug in the TMPR3927f, TMPR3927af, TMPR3927bf and TMPR3927c. w there are two w 1) disable the the broken master check register to 0. (masters a, b, c and d). s there is - 36 - 4 .com u datasheet tx3927 ert-tx3927-019 product types: TMPR3927f, TMPR3927af, TMPR3927bf, TMPR3927cf conditions when an sio overrun error is detected by checking the oers bit in the status change interrupt status register (siscisr) there are two way to detect this error. one is by checking the oers bit by software. the other is by setting the stie field of the dma/interrupt control register (sidicr) to 1***** . outline writing a 0 to the oers bit in the status change interrupt status register (siscisr) does not clear it. the oers bit can be cleared by writing a 0 to the ubrkd bit in the siscisr register. symptom after initializing the sio, the oers bit is set to 1 upon the first overrun error. (defect 1) writing a 0 to the oers bit does not clear it. thus, once an overrun error occurs, the state of overrun detection is not correctly reflected to the oers bit. consequently, subsequent overrun errors can't be detected by checking the oers bit. (defect 2) the oers bit is cleared by a writing 0 to the ubrkd bit in the siscisr register. workarounds use the uoer bit in the dma/interrupt status register (sidisr) to detect ove rrun errors. (even in the presence of this bug, overrun errors can be handled through the uoer bit.) according to the sio specification, a software reset should be performed when an overrun error occurs. a software reset can be performed by writing a 1 to th e swrst bit in the fifo control register (sifcr). status the applicable products will not be corrected. - 37 - 4 .com u datasheet tx3927 summary of the differences among versions of the tx3927 errata no. description tx3927f tx 3927af tx3927bf tx3927cf ? prid value 0x0000_2240 0x0000_2241 0x0000_2242 ? crir value 0x3927_0032 0x3927_0040 0x3927_0040 ? ddrad bit of lbc register in pci controller no yes yes yes 001 moisture-proof packing 002 electrostatic discharge 003 supply voltage when tlb is on 004 pci stop * signal 005 clock output upon reset 006 branch-likely instruction 007 pci configuration read 008 romc in half-speed mode 009 snooping in doze mode 010 cache instruction in write-back mode 011 pci read access 012 never time out of pcic 013 accesses to pcic reserved area 014 pcic 3-byte data access 015 cpu lock after a bus error 016 sio break detection 017 accesses to the pcic r/wl bits 018 pci broken master checking feature 019 detection of sio overrun errors note 1: legned used in the summary table : applies to this device. : modified in this device. : modified partly in this device. note 2: refer to the respective sections for details. - 38 - 4 .com u datasheet |
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